1. Field of the Invention
The present invention relates to a layout designing method for a semiconductor integrated circuit device, and particularly to an improvement of a layout designing method for an LSI by a CMOS standard cell method.
2. Description of the Background Art
According to a recent general classifying method, LSIs may be classified into custom LSIs and semicustom LSIs based on an LSI layout design. The custom LSIs may be defined as LSIs of which whole constructions or internal blocks are designed specially for intended particular LSIs. The semicustom LSIs may be defined as LSIs which are designed using libraries in which layout patterns already designed as common circuits are registered. According to this definition, a standard cell method can be classified into a designing method for a semicustom LSI.
In the standard cell method, standard circuit block cells are designed in advance and registered in a cell library for the use in the design of LSIs, and this method is one kind of designing method for the semicustom LSIs. Each circuit block cell is disposed by means of an automatic arranging and interconnecting program of a CAD system. The standard cells which are standard circuit block cells registered in the library usually have layout patterns in which logical circuits such as simple logical gates and flip-flops are designed in advance. Once designed, these standard layout patterns are registered in a data base after their correct operations are verified by simulation and/or experiment. Thereby, the cell library is formed. These standard layout patterns have configurations in which heights are constant and widths are variable. As described above, in the layout design of the LSI by the standard cell method, standard layout patterns are selected from the library and interconnections between the layout patterns are formed by the CAD system.
A prior art example of the layout designing method for the LSIs by the CMOS standard cell method is disclosed in "Principles of CMOS VLSI Design; A System Perspective", Neil H. E. Weste et al., pp 193-195. The prior art method for designing an LSI layout by the CMOS standard cell method will be described below with reference to the figures.
FIG. 7 is a flow chart showing a conventional method for designing the LSI layout by the standard cell method. Referring to FIG. 7, a predetermined logical circuit diagram to be designed is first entered in a CAD system. Here, the layout designing method will be further described with respect to a logical circuit diagram which is shown in FIG. 8 as an example of the entered logical circuit diagram.
In the logical circuit diagram shown in FIG. 8, data is entered from I1-I6 appropriately processed and the data is output from OUT. Tables 1 and 2 are truth tables related to this logical circuit diagram.
TABLE 1 ______________________________________ I4 I2 I3 Q .sup.-- Q ______________________________________ 0 0 0 unchanged 0 0 1 0 1 0 ______________________________________ 0 1 1 0 1 ______________________________________ 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 ______________________________________ 1 1 1 inhibited ______________________________________
TABLE 2 ______________________________________ I6 I1 I5 OUT ______________________________________ 0 * 0 .sup.-- Q 1 1 1 0 * Q 1 * 1 ______________________________________
In Table 1, a term "unchanged" indicates a state in which an output state does not change. A term "inhibited" indicates inhibition of input of this combination. In Table 2, a sign "*" indicates 1 or 0. "Q" and "Q" indicate that outputs in the truth table shown as the table 1 are output as they are.
The entered logical circuit diagram is formed of circuit blocks G1-G5. An internal logical circuit diagram of the circuit block G2 is shown in FIG. 9. The internal logical circuit diagram of the circuit block G5 is shown in FIG. 10. The logical circuit diagram in FIG. 8 is shown at a logical gate level in FIG. 11. Further, the logical circuit diagram in FIG. 11 is shown as a circuit diagram at a transistor level in FIG. 12.
When the logical circuit diagram shown in FIG. 8 is entered in the CAD system, the logical circuit diagram is divided into logical function units, i.e., the circuit blocks G1-G5. These circuit blocks G1-G5 have been previously designed as standard circuit block cells, and have been registered in a cell library of the CAD system as layout patterns which correspond to respective circuit block cells. Therefore, the standard cells respectively corresponding to the logical function units, i.e., circuit blocks G1-G5 can be selected as the layout cells from the library.
The layout cells corresponding to the circuit blocks G1, G2, G3 (G4) and G5 are shown in FIGS. 13A, 14A, 15A and 16A, respectively. Circuit diagrams at the transistor level corresponding to these circuit blocks G1, G2, G3 (G4) and G5 are shown in FIGS. 13B, 14B, 15B and 16B, respectively.
Referring to FIGS. 13A and 13B, the circuit block G1 is formed of p-channel MOS transistors T11, T12 and T13 and n-channel MOS transistors T14, T15 and T16. The respective MOS transistors are interconnected through first interconnections. Input terminals A and B as well as an output terminal O are disposed at an upper (second) interconnection which is connected to the first interconnection through a through hole. A layout cell corresponding to the circuit block G1 is a standard layout cell having a logical function of an AND gate.
Referring to FIGS. 14A and 14B, the circuit block G2 is formed of p-channel MOS transistors T31, T32, T35 and T36 as well as n-channel MOS transistors T33, T34, T37 and T38. P-regions, n-regions and gate electrode interconnections of the respective MOS transistors are connected together by the first interconnections through contact holes. These first interconnections are connected to upper second interconnections via through holes. Input terminals R and S as well as output terminals Q and Q are disposed at the second interconnections. In the figure, a power supply interconnection V.sub.DD is disposed above the p-channel MOS transistors T31, T32, T35 and T36. In the figure, a ground interconnection GND is disposed below the n-channel MOS transistors T33, T34, T37 and T38. In this manner, a standard layout cell of the circuit block G2, i.e., flip-flop gate is formed.
FIG. 15A shows a standard layout cells of the circuit blocks G3 and G4, i.e., OR gates, Referring to FIGS. 15A and 15B, the circuit blocks G3 and G4 are formed of p-channel MOS transistors T21, T22 and T23 as well as n-channel MOS transistors T24, T25 and T26. Similarly to the layout cells of the circuit blocks G1 and G2, p-regions, n-regions and gate electrode interconnections of respective MOS transistor are interconnected by first interconnections through contact holes, and second interconnections are connected to the first interconnections via through holes. The second interconnections are provided with input terminals A and B as well as an output terminal O.
Referring to FIGS. 16A and 16B, the circuit block G5, i.e., a selector circuit is formed of p-channel MOS transistors T41, T42, T43, T44, T49, T51 and T52 as well as n-channel MOS transistors T45, T46, T47, T48, T50, T53 and T54. P-channel regions, n-channel regions and gate electrode interconnections of the respective MOS transistors are connected by first interconnections through contact holes, and second interconnections are connected to the first interconnections via through holes. Input terminals A, SA and B as well as an output terminal O are provided in the second interconnections.
As described above, in the layout cell of each of the circuit blocks G1-G5, the input terminals and the output terminal(s) are disposed at the upper and lower sides of each layout cell in the figure. Further, as can be seen in FIGS. 13A, 14A, 15A and 16A, each layout cell has the configuration in which the height h is constant and the lateral width is variable. This configuration of the layout cell is determined to meet a demand for easier arrangement of the layout cells and easier interconnections of the layout cells in the layout designing for the LSI.
These layout cells are arranged in accordance with the logical circuit diagram shown in FIG. 8. FIG. 17A shows an arrangement of the layout cells.
These layout cells are arranged in accordance with the logical circuit diagram shown in FIG. 8. FIG. 17A shows an arrangement of the layout cells. The layout cells of the circuit blocks G2, G3 and G4 are disposed in an upper side in the figure, and the layout cells of the circuit blocks G1 and G5 are disposed at the lower side in the figure. A region 1000 between a group of the layout cells disposed at the upper side and a group of the layout cells disposed at the lower side is used for interconnections between the layout cells.
Second interconnections between the layout cells are formed as shown in FIG. 17B. A pattern of the second interconnections has a configuration in which each second interconnection provided with an input terminal or an output terminal of each layout cell extends through the region 1000 between the upper and lower layout groups.
Thereafter, first interconnections between the layout cells are formed, as shown in FIG. 17C. A pattern of the first interconnections is formed such that the pattern of the second interconnections which has been formed as shown in FIG. 17B may be connected to the first interconnections via through holes. The patterns of these first and second interconnections are formed in accordance with the logical circuit diagram shown in FIG. 8 by an automatic arranging and interconnecting program of the CAD system.
Finally, as shown in FIG. 17D, compaction is executed for compacting the interconnection region 1000 between the upper layout cell group and the lower layout cell group. In this manner, the layout design of the LSI is performed by the standard cell method.
Since the layout designing method by the conventional standard cell method is performed as described above, even layout cells located in the same row are interconnected using the interconnection region 1000. Specifically, as shown in FIG. 17D, an interconnection 305 between the layout cells of the circuit blocks G2 and G4 which are located in the same row is disposed using the interconnection region 1000 between the upper layout cell group and the lower layout cell group. The interconnection region 1000 is also used by an interconnection 309 between the layout cells of the circuit blocks G2 and G3 which are located in the upper layout cell group. This increases lengths of the interconnections, and thus reduces an operation speed of the LSI thus designed.